1. Field of the Invention
This invention relates to a pulse generating apparatus applied to semiconductor circuits, and more particularly to a pulse generating apparatus generating a pulse at an output terminal in response to conditions of a control signal and an input signal.
2. Description of the Prior Art
A related art of a pulse generating apparatus typically includes a delay circuit having a plurality of inverters IV1 to IV3 which are connected in series to each other by using resistors R1 and R2 and capacitors C1 and C2, so that an output signal with an inphase or antiphase to an input signal is output as depicted in FIG. 1 (an antiphase signal is output in FIG. 1).
As depicted in FIG. 2, a related art of the pulse generating apparatus having the delay circuit includes a delay circuit 10 for delaying an external input signal A0 during a constant time, and a NAND gate 12 for performing a NAND operation by receiving both the external input signal A0 and an output A1 (delayed external signal) from the delay circuit 10.
According to the related art of the pulse generating apparatus, if the input signal A0 shown in FIG. 3a is inputted to one terminal of the NAND gate 12, and an opposite and delayed signal A1 through the delay circuit 10 as shown in FIG. 3b is inputted to the other terminal of the NAND gate 12, a logic low pulse is generated when the input signal A0 of a low level is changed to a high level as the result of a logical condition for the input signal combination in the NAND gate 12, as shown in FIG. 3c.
FIG. 4 is a circuit diagram showing the other related art of a pulse generating apparatus. As depicted in FIG. 4, the other related art of the pulse generating apparatus includes a delay circuit 10 for delaying an input signal B0 during a constant time, and a NOR gate 14 for performing a NOR gate operation upon receiving the input signal B0 and the output signal B1 from the delay circuit 10.
According to the other related art of the pulse generating apparatus, the input signal B0 as shown in FIG. 5a is inputted to a terminal of the NOR gate 14, and a delayed signal B1 with antiphase as shown in FIG. 5b is inputted to the other terminal of the NOR gate 14, thereby generating a logic high pulse when the input signal B0 of a high level is changed to a low level as the result of the logical condition for the input signal combination in the NOR gate 14 as shown in FIG. 5c.
As described above, there is a problem in that the related art of the pulse generating apparatus has been used for connecting additional capacitors having too large an area to extend the width of a required pulse signal, and other gates have been required to control the width of the pulse signal. Accordingly, the total area of the related art of the pulse generating apparatus may be increased as a result of the above reasons.